Semiconductor constructions containing integrated memory can often be considered to comprise three distinct regions. One of the regions is a memory array region which contains a large number of tightly-packed lines (wordlines and bitlines) and data-storage structures (such as, for example, capacitors in dynamic random access memory (DRAM)); a peripheral region containing loosely-packed structures and having logic circuitry utilized for accessing memory cells associated with the memory array; and a pitch region where loosely-packed circuitry from the peripheral region is brought into a tightly-packed configuration to interface with the circuitry of the tightly-packed memory array region. For instance, a typical series of wordlines can be considered to have segments that are tightly-packed within the memory array region, segments loosely-packed within the peripheral region, and segments within the pitch region which connect the segments of the peripheral region to the segments of the memory array region. The pitch region thus makes the transition from the loosely-packed configuration of the peripheral region to the tightly-packed configuration of the memory array region.
Although there typically are not absolute boundaries between the peripheral region and the pitch region, or between the pitch region and the memory array region, persons of ordinary skill in the art generally recognize that the three regions exist across a semiconductor wafer comprising integrated memory, and can agree on the general locations of the three regions relative to one another.
FIG. 1 shows a fragment of a semiconductor wafer construction 10 illustrating the relationships between a memory array region 12, pitch region 14 and peripheral region 16. An approximate boundary between the memory array region and pitch region is illustrated with the dashed line 13, and an approximate boundary between the pitch region and the peripheral region is illustrated with a dashed line 15.
The construction 10 comprises a substrate 18 having a plurality of lines 20, 22, 24, 26, 28, 30, 32, 34, 36, and 38 extending thereover. The lines have segments within the memory array region 12, and such segments can correspond to, for example, either wordlines or bitlines. The segments of the lines within the memory array region 12 are tightly-packed, and typically would be packed to about the limits achievable with the fabrication process utilized to form the lines. Lines 20, 22, 24, 26, 28, 30, 32, 34, 36, and 38 also have segments extending over peripheral region 16, and such segments are relatively loosely-packed as compared to the packing across memory array region 12.
The pitch region comprises a transition from loosely-packed structures along the boundary 15 with the peripheral region to tightly-packed structures along the boundary 13 with the memory array region.
FIG. 2 illustrates a cross-sectional view through the line segments 20, 22 and 24. Such view shows that the line segments comprise electrically conductive core regions 40 surrounded by electrically insulative shells 42 (the shells can also be referred to as liners or coverings). The core regions 40 can comprise any suitable electrically conductive composition or combination of compositions. For instance, the electrically-conductive material of the core regions 40 can comprise various metals, metal compositions and/or conductively-doped semiconductor materials (such as, for example, conductively-doped silicon). In some aspects, the core regions 40 can comprise stacks of electrically-conducted material, such as, for example, stacks containing various metals and/or metal compositions over conductively-doped semiconductor material.
The electrically insulative shell 42 can comprise any suitable electrically insulative composition or combination of compositions. For instance, the electrically-insulative shell can comprise, consist essentially of, or consist of silicon nitride, silicon dioxide, and/or silicon oxynitride. In some aspects, the shell 42 will comprise sidewall spacers joining an electrically insulative cap, as is known to persons of ordinary skill in the art.
The substrate 18 is shown comprising an electrically-insulative layer 44 over a bulk material 46. Electrically insulative layer 44 can, for example, comprise, consist essentially of, or consist of silicon dioxide; and bulk material 46 can comprise, consist essentially of, or consist of monocrystalline silicon which may or may not be lightly background-doped with appropriate dopant. The combination of materials 46 and 44 can be referred to as a semiconductor substrate in some aspects of the invention, or in other aspects it can be material 46 alone which is referred to as a semiconductor substrate, or in yet other aspects the term semiconductor substrate can comprise materials 44 and 46 together with other materials. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Although the shown substrate 18 comprises a bulk material 46, it is to be understood that the material 46 can instead comprise various levels of integrated circuitry which are formed beneath the lines 20, 22 and 24. Specifically, as is known to persons of ordinary skill in the art, semiconductor devices will typically comprise multiple layers of integrated circuitry stacked over one another. The shown processing of FIGS. 1 and 2 can be utilized to form a first level of integrated circuitry over a semiconductive-material wafer, or can be utilized to form a later level which is formed over previous levels.
In subsequent processing, additional levels can be formed over the structure of FIGS. 1 and 2. For instance, FIG. 3 shows the construction of FIG. 2 after dielectric filler material 48 is provided over and between lines 20, 22 and 24. The dielectric filler material can comprise any suitable composition or combination of compositions, and in particular aspects will comprise, consist essentially of, or consist of one or more of spin-on-dielectric (SOD), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG) and silicon dioxide. The dielectric filler material is shown having a planarized upper surface 49, which can be formed by, for example, chemical-mechanical polishing. In subsequent processing, another layer of integrated circuitry can be formed on top of planarized upper surface 49.
FIG. 4 shows a top view of the construction 10 at the processing stage of FIG. 3, and shows that the dielectric filler material 48 can extend over the memory array region 12, pitch region 14 and peripheral region 16.
A continuing goal of semiconductor device fabrication is to improve device performance, and preferably to accomplish such improvement without substantial modification of existing semiconductor fabrication processes that would require significant investment in additional equipment. Thus, it would be desirable to develop methodologies for improving on constructions of the type described in FIGS. 1-4 without introducing deviations that would require significant investment in new equipment for existing fabrication processes.